Investigation of a Neural Network Decomposition by Proteus Design Suite

The division of a monolithic neural network into blocks with their implementation on programmable logic within the framework Fog computing concept is considered. It assumed that considering possible reconfiguration performed logic: field-programmable gate array, FPGA (complex device, CPLD), System-on-a-Chip, SoC or System-in-Package, SiP. article explores such an in Proteus Design Suite based ATMega32 microcontrollers. Modeling confirms efficiency developed decomposition method. research was carried out under RFBR grant 20-37-90036 (Method synthesizing recognition devices for implementing mode).